Cadence Q DRIVE SERIES Manuel d'utilisateur télécharger pdf (Page 10)

C. Optimization

One last thing you should experiment is to optimize your gate-level netlist to reduce the

propagation delay between the flip-flop boundaries and perhaps to reduce its real estate

foot print on the chip (circuit area).

(a) Viewing unoptimized cells after the synthesis:

Before starting to optimize the top-level schematic, my_design, view the contents of your

unoptimized full adder.

On the top-level schematic, my_design, find your full adder, and double click the

full_adder module, view and print your unoptimized full adder schematic.

(b) Optimize the design:

To Optimize the design, type:

ac_shell> do_optimize

Now, double click the newly created full_adder module.

Print and compare the difference between the unoptimized and optimized full adder

schematics in terms of propagation delays and area.

(d) Exit ac_shell:

Type:

ac_shell> exit.

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Cadence Q DRIVE SERIES Manuel d'utilisateur Page 10