Cadence M7000 Manuel d'utilisateur

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®
Altera Corporation 57
MAX 7000
Programmable Logic
Device Family
February 1998, ver. 5.01 Data Sheet
A-DS-M7000-05.01
Features...
High-performance, EEPROM-based programmable logic devices
(PLDs) based on second-generation Multiple Array MatriX (MAX)
architecture
5.0-V in-system programmability (ISP) via standard Joint Test Action
Group (JTAG) interface (IEEE Std. 1149.1-1990) available in
MAX 7000S devices
Built-in JTAG boundary-scan test (BST) circuitry in MAX
®
7000S
devices with 128 or more macrocells
Complete EPLD family with logic densities ranging from 600 to 5,000
usable gates (see Table 1)
5-ns pin-to-pin logic delays with up to 178.6-MHz counter
frequencies (including interconnect)
PCI-compliant devices available
Open-drain output option in MAX 7000S devices
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Note:
(1) Values in parentheses are for low-voltage EPM7032V devices.
Table 1. MAX 7000 Device Features
Note (1)
Feature EPM7032
EPM7032V
EPM7032S
EPM7064
EPM7064S
EPM7096 EPM7128E
EPM7128S
EPM7160E
EPM7160S
EPM7192E
EPM7192S
EPM7256E
EPM7256S
Usable
gates
600 1,250 1,800 2,500 3,200 3,750 5,000
Macrocells 32 64 96 128 160 192 256
Logic array
blocks
2 4 6 8 101216
Maximum
user I/O pins
36 68 76 100 104 124 164
t
PD
(ns) 6 (12) 5 7.5 6 6 7.5 7.5
t
SU
(ns) 5 (10) 4 6 5 5 6 6
t
FSU
(ns) 2.5 (n/a) 2.5 3 2.5 2.5 3 3
t
CO1
(ns) 4 (7) 3.5 4.5 4 4 4.5 4.5
f
CNT
(MHz) 151.5 (90.9) 178.6 125 151.5 151.5 125 125
Includes
MAX 7000E &
MAX 7000S
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Résumé du contenu

Page 1 - MAX 7000

® Altera Corporation 57 MAX 7000 Programmable LogicDevice Family February 1998, ver. 5.01 Data Sheet A-DS-M7000-05.01 Features... High-performance

Page 2

66 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFor registered functions, each macrocell flipflop can be individually program

Page 3

Altera Corporation 67MAX 7000 Programmable Logic Device Family Data SheetShareable ExpandersEach LAB has 16 shareable expanders that can be viewed as

Page 4 - Note (2)

68 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetThe MAX+PLUS II Compiler can allocate up to 3 sets of up to 5 parallel expand

Page 5

Altera Corporation 69MAX 7000 Programmable Logic Device Family Data SheetProgrammable Interconnect ArrayLogic is routed between LABs via the programm

Page 6 - Description

70 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 8. I/O Control Block of MAX 7000 DevicesNote:(1) The open-drain output

Page 7 - Altera Corporation 63

Altera Corporation 71MAX 7000 Programmable Logic Device Family Data SheetWhen the tri-state buffer control is connected to ground, the output is tri-

Page 8 - Macrocells

72 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetOutput ConfigurationMAX 7000 device outputs can be programmed to meet a variet

Page 9 - Altera Corporation 65

Altera Corporation 73MAX 7000 Programmable Logic Device Family Data SheetProgramming with External HardwareMAX 7000 devices can be programmed on 486-

Page 10 - Expander Product Terms

74 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetfGo to Application Note 39 (JTAG Boundary-Scan Testing in Altera Devices) for

Page 11 - Parallel Expanders

Altera Corporation 75MAX 7000 Programmable Logic Device Family Data SheetFigure 9. MAX 7000 AC Test ConditionsQFP Carrier & Development SocketMAX

Page 12 - Figure 6. Parallel Expanders

58 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet ...and More Features Programmable power-saving mode for 50 % or greater

Page 13 - I/O Control Blocks

76 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetMAX 7000 5.0-V Device Recommended Operating Conditions MAX 7000 5.0-V D

Page 14 - Note (1)

Altera Corporation 77MAX 7000 Programmable Logic Device Family Data SheetMAX 7000 5.0-V Device Capacitance: MAX 7000E Devices Note (11)MAX 7000

Page 15 - Altera Corporation 71

78 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet3.3-V EPM7032V DevicesEPM7032V devices are high-performance MAX 7000 devices

Page 16 - Configuration

Altera Corporation 79MAX 7000 Programmable Logic Device Family Data SheetFigure 11. Power-Down Mode Switching WaveformsThe switching waveforms for EP

Page 17

80 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetAll power-down/chip-enable timing parameters are computed from external input

Page 18 - Generic Testing

Altera Corporation 81MAX 7000 Programmable Logic Device Family Data SheetEPM7032V 3.3-V Device DC Operating Conditions Notes (4), (5)EPM7032V 3

Page 19 - Conditions

82 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 12. EPM7032V Output Drive CharacteristicsTiming ModelMAX 7000 device t

Page 20 - 76 Altera Corporation

Altera Corporation 83MAX 7000 Programmable Logic Device Family Data SheetThe timing characteristics of any signal path can be derived from the timing

Page 21

84 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 14. Switching WaveformsCombinatorial ModeInput PinI/O PinPIA DelayShar

Page 22 - EPM7032V

Altera Corporation 85MAX 7000 Programmable Logic Device Family Data SheetMAX 7000 AC Operating Conditions Notes (1), (2)

Page 23 - Altera Corporation 79

Altera Corporation 59MAX 7000 Programmable Logic Device Family Data Sheet Note: (1) All information on MAX 7000S devices is preliminary. Contact Al

Page 24 - 80 Altera Corporation

86 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetInternal Timing ParametersSpeed Grade-5 -6 -7Symbol Parameter Conditions Min

Page 25 - Notes to tables:

Altera Corporation 87MAX 7000 Programmable Logic Device Family Data Sheet External Timing ParametersSpeed GradeMAX 7000E (-10P)MAX 7000S (-10)MAX

Page 26 - Timing Model

88 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Internal Timing ParametersSpeed GradeMAX 7000E (-10P)MAX 7000S (-10)MAX 700

Page 27 - Altera Corporation 83

Altera Corporation 89MAX 7000 Programmable Logic Device Family Data Sheet External Timing ParametersSpeed GradeMAX 7000E (-12P) MAX 7000 (-12)MAX

Page 28 - Array Clock Mode

90 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetInternal Timing ParametersSpeed GradeMAX 7000E (-12P) MAX 7000 (-12)MAX 7000E

Page 29 - External Timing Parameters

Altera Corporation 91MAX 7000 Programmable Logic Device Family Data SheetExternal Timing ParametersSpeed Grade-15 -15T -20Symbol Parameter Conditions

Page 30 - Internal Timing Parameters

92 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetInternal Timing ParametersSpeed Grade-15 -15T -20Symbol Parameter Conditions

Page 31

Altera Corporation 93MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) These values are specified under the “MAX 7000 5.0-V Dev

Page 32

94 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetEPM7032V AC Operating Conditions Note (1) Notes to tables:(1) These va

Page 33

Altera Corporation 95MAX 7000 Programmable Logic Device Family Data SheetMAX 7000 3.3-V Device Power-Down/Chip-Enable Timing ParametersPower Consumpt

Page 34

60 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet Notes: (1) Available in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices

Page 35

96 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetThe parameters in this equation are shown below:MCTON= Number of macrocells w

Page 36

Altera Corporation 97MAX 7000 Programmable Logic Device Family Data SheetFigure 15 shows typical supply current versus frequency for MAX 7000 devices

Page 37

98 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 15. ICC vs. Frequency for MAX 7000 Devices (Part 2 of 2)VCC = 5.0 VRoo

Page 38

Altera Corporation 99MAX 7000 Programmable Logic Device Family Data SheetFigure 16 shows typical supply current versus frequency for MAX 7000S device

Page 39 - Consumption

100 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 16. ICC vs. Frequency for MAX 7000S Devices (Part 2 of 2)Information

Page 40 - Equation Constants

Altera Corporation 101MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) The 44-pin PQFP package is not offered for EPM7032S dev

Page 41 - Figure 15. I

102 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 9. EPM7064 & EPM7064S Dedicated Pin-Outs Note (1)Dedicated P

Page 42

Altera Corporation 103MAX 7000 Programmable Logic Device Family Data SheetTable 10. EPM7064 & EPM7064S I/O Pin-Outs (44-Pin J-Lead, 44-Pin TQFP

Page 43 - Figure 16. I

104 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) The GCLK2 function is available in MAX 7000S devices onl

Page 44 - Pin-Outs

Altera Corporation 105MAX 7000 Programmable Logic Device Family Data SheetTable 12. EPM7096 Dedicated Pin-Outs Dedicated Pin 68-Pin J-Lead 84-Pin

Page 45

Altera Corporation 61MAX 7000 Programmable Logic Device Family Data Sheet Notes: (1) Contact Altera for up-to-date information on available device p

Page 46

106 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet33 C 33 41 39 49 D 36 44 4234 C – – – 50 D – – –35 C 32 40 38 51 D 37 45 433

Page 47

Altera Corporation 107MAX 7000 Programmable Logic Device Family Data SheetTable 14. EPM7128E & EPM7128S Dedicated Pin-Outs Dedicated Pin 84

Page 48

108 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 15. EPM7128E & EPM7128S I/O Pin-Outs (Part 1 of 2) Note (2)M

Page 49

Altera Corporation 109MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) A complete thermal analysis should be performed before

Page 50

110 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 16. EPM7160E & EPM7160S Dedicated Pin-Outs Note (1)Dedicated

Page 51 - 160-Pin PQFP

Altera Corporation 111MAX 7000 Programmable Logic Device Family Data Sheet13 A – – – 146 29 B – – – 714 A – 93 95 145 30 B – 2 4 16015 A – – – – 31 B

Page 52

112 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetNote to tables:(1) For MAX 7000S devices, this pin may function as either a

Page 53

Altera Corporation 113MAX 7000 Programmable Logic Device Family Data SheetTable 18. EPM7192E & EPM7192S Dedicated Pin-Outs Dedicated Pin160

Page 54

114 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet49 D D15 33 65 E B12 45 81 F D8 6050 D – – 66 E – – 82 F – –51 D E15 31 67 E

Page 55

Altera Corporation 115MAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) This package is not offered for EPM7192S devices.(2) Fo

Page 56

62 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetThe MAX 7000 family provides programmable speed/power optimization. Speed-cri

Page 57

116 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetTable 20. EPM7256E & EPM7256S Dedicated Pin-Outs Dedicated Pin 160

Page 58

Altera Corporation 117MAX 7000 Programmable Logic Device Family Data Sheet14 A – U13 166 30 B – N15 15015 A – – – 31 B – – –16 A 154 T14 167 32 B 4 T

Page 59

118 Altera CorporationMAX 7000 Programmable Logic Device Family Data Sheet97 G 30 E16 119 113 H 60 C9 7998 G – – – 114 H – – –99 G 29 F17 120 115 H 59

Page 60 - Note (3)

Altera Corporation 119MAX 7000 Programmable Logic Device Family Data Sheet161 K 91 F3 38 177 L 61 B9 78162 K – – – 178 L – – –163 K 92 F1 37 179 L 62

Page 61

120 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetNotes to tables:(1) A complete thermal analysis should be performed before c

Page 62

Altera Corporation 121MAX 7000 Programmable Logic Device Family Data SheetFigure 17. 44-Pin Package Pin-Out DiagramPackage outlines not drawn to scal

Page 63

122 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 18. 68-Pin Package Pin-Out DiagramPackage outlines not drawn to scale

Page 64

Altera Corporation 123MAX 7000 Programmable Logic Device Family Data SheetNotes:(1) Pins 6, 39, 46, and 79 are no-connect (N.C.) pins on EPM7096, EPM

Page 65 - 44-Pin TQFP

124 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetFigure 22. 192-Pin Package Pin-Out DiagramPackage outline not drawn to scale

Page 66 - 68-Pin J-Lead

Altera Corporation 125MAX 7000 Programmable Logic Device Family Data SheetRevision HistoryThe information contained in the MAX 7000 Programmable Logi

Page 67

Altera Corporation 63MAX 7000 Programmable Logic Device Family Data SheetFigure 1. EPM7032, EPM7032V, EPM7064 & EPM7096 Device Block DiagramFigur

Page 68 - Pin 105Pin 53

Copyright © 1995, 1996, 1997, 1998 Altera Corporation, 101 Innovation Drive, San Jose, CA 95134, USA, all rights reserved.By accessing this informati

Page 69 - Revision

64 Altera CorporationMAX 7000 Programmable Logic Device Family Data SheetLogic Array BlocksThe MAX 7000 device architecture is based on the linking of

Page 70 - Legal Notice

Altera Corporation 65MAX 7000 Programmable Logic Device Family Data SheetThe macrocell of MAX 7000E and MAX 7000S devices is shown in Figure 4.Figure

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